1. Field of the Invention
This invention relates to the field of computer processors and, more particularly, to computer processors executing variable-length instructions.
2. Description of the Related Art
Computer processor architectures may generally be classified as either complex instruction set computing (CISC) architectures or reduced instruction set computing (RISC) architectures. CISC architectures (e.g., the x86 processor architecture) specify instruction sets including high level, relatively complex instructions. Processors implementing CISC architectures often decompose complex instructions into multiple simpler operations which may be more readily implemented in hardware. RISC architectures, on the other hand, typically specify instruction sets including low level, relatively simple instructions. Complexities associated with the CISC approach are removed, resulting in simpler hardware implementations. Such simpler hardware implementations are often capable of higher frequency operation. The MIPS architecture is an exemplary RISC architecture.
Although not necessarily a defining feature, variable-length instruction sets have often been associated with CISC architectures, while fixed-length instruction sets have been associated with RISC architectures. Variable-length instruction sets use dissimilar numbers of data units (e.g., bytes) to encode instructions as well as to specify addressing modes for the instructions, etc. Generally speaking, variable-length instruction sets attempt to pack instruction information as efficiently as possible into one or more bytes representing each instruction. Conversely, fixed-length instruction sets employ the same number of data units (e.g., bytes) for each instruction. Typically, a small number of instruction formats including fixed fields of information are defined. Decoding of fixed-length instructions is thereby simplified to routing bits corresponding to each fixed field to logic designed to decode the fields.
As each instruction of a fixed-length instruction set includes a fixed number of bytes, locating instructions is simplified as well. The location of instructions subsequent to a particular instruction is implied by the location of the particular instruction (i.e. as fixed offsets from the location of the particular instruction). Conversely, locating a second variable-length instruction requires locating the end of the first variable-length instruction; locating a third variable-length instruction requires locating the end of the second variable-length instruction, etc. Still further, variable-length instructions lack the fixed field structure of fixed-length instructions. Decoding is further complicated by the lack of fixed fields.
RISC architectures employing fixed-length instruction sets suffer from problems not generally applicable to CISC architectures employing variable-length instruction sets. Because each instruction is fixed length, certain relatively simple instructions may waste memory space by occupying more bytes than needed to convey instruction information. In contrast, variable-length instruction sets typically pack instruction information into the smallest possible number of bytes.
Still further, since RISC architectures do not include the more complex instructions employed by CISC architectures, the number of instructions in a program coded with RISC instructions may be larger than the number of instructions employed in the same program coded in with CISC instructions. Each of the more complex instructions coded in the CISC version of the program is replaced by multiple instructions in the RISC version of the program. Therefore, the RISC version of a program often occupies significantly more memory than the CISC version of the program. Correspondingly, a greater instruction bandwidth is required between memory storing the program and the processor is needed for the RISC version of the program than for the CISC version of the program.
In the past, the MIPS RISC architecture supported only a 32-bit MIPS instruction set including fixed-length, 32-bit MIPS instructions. More recently, the MIPS architecture has been expanded to include an optional MIPS16 application-specific extension (ASE). The MIPS16 ASE defines both 16-bit MIPS16 instructions and 32-bit MIPS16 instructions. The MIPS16 instruction set is thus by definition a variable-length instruction set. Each “compressed” MIPS16 instruction has a corresponding “noncompressed” 32-bit MIPS instruction, and translation hardware is commonly used to translate MIPS16 instructions to corresponding 32-bit MIPS instructions for execution by a MIPS processor. The MIPS16 instruction set allows instructions to be encoded using fewer bits, and the MIPS16 version of a program often occupies significantly less memory than the 32-bit MIPS version of the same program.
A processor implementing the MIPS RISC architecture may execute instructions (i.e., code) including 32-bit MIPS instructions, MIPS16 instructions, or both 32-bit MIPS instructions and MIPS16 instructions. In the simplest implementation, 16-bit MIPS16 instructions following non-aligned MIPS16 instructions must be fetched from an instruction cache twice (i.e., refetched). Such duplicate fetches have two detrimental effects. First, even when the refetched instructions are found in an instruction cache, the duplicate fetches increase the required number of instruction cache reads, thus increasing the amount of electrical power dissipated by instruction cache logic. This increased electrical power dissipation tends to become very significant at higher clock frequencies. Second, when a refetched instruction is not found in the instruction cache, the refetched instruction must be re-fetched from an external memory. This creates a problem as bus interface logic used to access the external memory is typically optimized for sequential fetches.
An ongoing need thus exists for processors having dynamically reconfigurable hardware capable of efficiently fetching both fixed-length instructions and variable-length instructions.